, computers.
I'm super excited about it because it is simpler than every other design I tried, but has many useful properties that every other attempt lacked:
- Keeps control signal separate from data
- 1 tick of delay, during all states: storing, holding, or passthrough
- Passthrough operation when R is high (does not accumulate sum)
- Timing is super simple, just holds the data signal that was present during the last tick that R was high.
- When R goes high again after holding data, updates the output on the very next tick with whatever was on the input on that tick
- Simple!
Also this design can be very easy to modify for slightly different behaviors. Like if you want to have the actual clock on the green wire (a signal that repeatedly ranges 0...n), just invert the conditionals on the 2 deciders, keeping all wiring the same, and you now have a latch that works with the clock signal directly (no need to pulse a single tick R=1)
For this blueprint, the data line is red wire (both input and output), and the control line is green wire. Everything can be wired to the top combinator.
One thing to watch out for is if you put any other signal on the red output wire, it will accumulate into the held data. If that is undesirable I think with some re-wiring you can eliminate that behavior at the cost of making a 2 tick-delay flip-flop.
- memory cell.jpg (578.74 KiB) Viewed 1552 times
