I've done some additional work on MK2 CPU in order to improve the throughput and responsiveness. The new MK3 has approx 30% better throughput and supports interrupts which should allow much better reaction to unanticipated events.
A brief video overview showing interrupt handling and explanation of the new asynchronous (clock less) mode of operation is available on YouTube https://www.youtube.com/watch?v=RUVZcV3-Kh4
For those who prefer static pictures I'm including a picture of MK3 overlaid with signal paths for a simple ( load immediate) instruction. Note that the color of the signal path indicates the tick in which it's active and the text besides the arrow shows the principal signals carried.
The instruction starts with address (A) generated in the Program Counter carried by the tan arrow to the memory location.
The following tick, memory cell releases bp (blue print i.e. instruction "load") and D (i.e. the operand) -yellow arrow carries it to the microcode.
The following tick, microcode releases (sg i.e. shotgun which zeroes accumulator, water and crude both used in generating the next address and virtual 1 which selects the ALU operation (i.e. load)
These signal with the exception of virtual 1, together with address (A) and data (D) exit the Instruction Decoder the following tick as depicted by the bright green arrows. A ,water and crude enter the program counter and are used to generate the new instruction address (teal arrow). D and shotgun enter the ALU where shotgun zeroes accumulator and D is delayed by one tick and then is multiplied by virtual 1 which just exited the instruction decoder. The result (of this multiplication is fed into accumulator and several deciders that generate signals used in subsequent branching (light and dark blue arrows).
Some other architectural changes in MK 3 include addition of 2 base registers used to generate a rough but much faster equivalent to the former indirect addressing mode.
The instruction set was enhanced to handle the added registers and now consists of:
program control : jump, beq,bgt,blt, bxrp,call,return
register load: ldi A,B,C,X,SP lad d+X+B|C pop A,B,X
store instructions: stor d+X+B|C push A,B,X
register moves: tab,tax,txa
Finally, the interrupt hardware (just below and to the right of "bp,D" label) captures about to be executed instruction address and forces a jump to an interrupt vector (which contains another jump to the actual interrupt routine) and releases the captured address when the interrupt handler routine executes RTI (return from interrupt).
I hope the above was fairly clear and informative. If you have any questions, I'll do my best to answer them