, computers.
- bus-demo.png (259.48 KiB) Viewed 192 times
- 1 timer device (up to 4 counters)
- 1 recipe lookup device (includes mock command button for testing)
- 1 ROM cell
- 6 RAM cells
- fCPU
- extra buttons to mock read/write commands for testing
Print comes pre-loaded with the demo program below.
Look at the description in each combr for more notes about it.
Each device on the bus is optional. Remove or mix in more as needed.
Each RAM cell can hold a dictionary (associative array) of many signal types. Each type holds a corresponding quantity, just like the output of any vanilla combinator. So one of these is an external equivalent to one of fCPU's internal memory cells that it uses for SIMD instructions. In fact its SIMD xmov instruction is used to read these external RAM cells.
For example, each RAM cell can hold all the ingredients to one recipe, together with their batch quantities. So the demo system has enough RAM for 6 complete recipes.
There's no limit to the number of memory cells or devices on one bus. There's no limit to the distance the bus could span. You could have one bus cover and operate your entire factory, but it might not be the best design.
Signal ! is the write command, and its quantity is the address of the device to write. Signal ? works the same for reading. The mock buttons demonstrate those manually. They can be used to verify you have your devices built correctly.
The green bus carries write data and all bus commands out from the fCPU. The red bus carries read data back to fCPU. Remember "red" looks like "read", and even sounds like it in the past tense.
The short red wire inside each RAM cell carries the memorized data of that cell only. Typically that includes the ! write command which put it there. That gets stripped off by the program after reading back. Having it there is actually handy because it shows you the cell's address when you hover on it.
Nearly any kind of circuitry or machinery can be controlled just by connecting it to the red wires inside one or more RAM cells. That's similar to peripheral control registers in a real microcontroller or a PC. That way the fCPU can carry on with other work while the controlled machines continue to receive their steady control signal. EDIT: In most cases it's actually better to connect your machines to the unoccupied green output of the memory cell (middle combr). That way incurs a delay because it won't output the new signal until the tick after the write command is removed (the command could last many ticks if your program stretches it out). But it avoids passing along to the machines any glitch pulses your program might accidentally output during the write command. Those come through the red wire from the write address decoder, but are then filtered out by the memory cell on its green output. Use the green wire by default if you can accept the delay, and want maximum stability and robustness. Go ahead and use the red wire instead if you can't tolerate any delay, and you can ensure your program won't output any unwanted signals during the write command. That's easy enough by running clr out immediately after giving the write command.
The timer device demonstrates i/o by simply connecting one memory cell to another in this case to use as an increment.
The recipe lookup device uses the exact same address decoders for writing and reading, but has no actual memory cell. It has the assembler machine in that place instead. It's unusual in that it requires write and read bus commands to run concurrently, because it has no memory cell to hold its state. Adding one (turning it into a regular RAM cell) could avoid that requirement.
The cell's address should be the same in all 3 combr's in the cell. Parameterized blueprints can help you lay new memory cells with the unique addresses they require. Then with care you can make one blueprint for an entire memory bank, then use it to lay several big memory banks with no address conflicts. Use a separate parameter for the bank's starting address or "base address".
Yes, you could easily have more fCPU's on the same bus. They'd naturally share the use of the other bus devices, and talk to each other too. That's a multi-master bus. But often one is enough, and that's easier because you don't have bus timing conflicts to avoid.
Another way to add a second fCPU is to put it on its own separate bus, forming its own complete system. Then connect the red wire from inside one of its RAM cells to a read address decoder on the first system's bus. That's good for simple and reliable one-way signaling. Repeat that in the opposite direction for 2-way signaling. You now have a network of multiple systems, just like real ones, but easier, for good gaming.
Enjoy! And be sure to post your accomplishments in this thread.
-- Demo program:
Code: Select all
; RAM and I/O bus demo program
; written by cb750mark 2025-12.
; for fCPU 0.4.39 and should work with later versions.
; clear all external RAM.
; this consists of a [virtual-signal=signal-exclamation-mark] write command to each address, with no data.
clr out
mov r1 10[virtual-signal=signal-exclamation-mark] ; clear all external mem.
:clr-next
mov out1 r1
inc r1
ble r1 15 :clr-next
clr out
; time the execution of certain instructions.
clr
mov out1 0[virtual-signal=signal-T] ; init T count to 0
mov out2 201[virtual-signal=signal-exclamation-mark] ; timer device's address is 201.
clr out
mov out1 1[virtual-signal=signal-T] ; set T increment to 1 to start timer.
mov out2 202[virtual-signal=signal-exclamation-mark]
clr out
; test instruction speed.
; WARNING: modifying program text in any way, including whitespace, can affect the 1 next run thereafter e.g. reading 6 ticks shorter than all other runs. 100% repeatable for any given program. something to do with fCPU internal init i guess.
; the following list all take 1 tick:
; emit (to mem)
; mov (to reg)
; clr out
emit mem1 5[item=pistol]
emit mem1 6[item=pistol]
emit mem1 7[item=pistol]
emit mem1 8[item=pistol]
clr out
mov out1 0[virtual-signal=signal-T] ; set T increment to 0 to stop timer.
mov out2 202[virtual-signal=signal-exclamation-mark]
; read elapsed time from T count.
mov out2 201[virtual-signal=signal-question-mark]
nop ; wait for read data to arrive.
fid r1 red [virtual-signal=signal-T]
; save result to external RAM cell 10
mov out1 r1
mov out2 10[virtual-signal=signal-exclamation-mark]
clr out
; read "qty of items to produce" from external ROM cell 401 to mem1.
clr out
mov out2 401[virtual-signal=signal-question-mark]
nop ; wait for read data to arrive.
xmov mem1 red
; write product quantities from mem1 to external RAM cell 12.
xmov out mem1
mov out2 12[virtual-signal=signal-exclamation-mark] ; scalar "out2" is output along with dictionary "out" by fCPU.
clr out
; get ingredients for electric furnace.
clr out
mov out1 1[item=electric-furnace] ; send goal product to asr.
mov out2 101[virtual-signal=signal-exclamation-mark] ; recipe device's address is 101.
; concurrent "write" and read is something we wouldn't normally do with a RAM cell etc but it's required for the recipe lookup device.
mov out3 101[virtual-signal=signal-question-mark]
slp 3 ; wait for ingts to arrive at input. 1 tick for write addressing, 1 for asr, 1 for read addressing. some may have already passed.
xmov mem1 red ; capture ingts to mem vector.
clr out
emit mem1 0[virtual-signal=signal-exclamation-mark] ; strip bus commands out of data.
emit mem1 0[virtual-signal=signal-question-mark]
; write ingts from mem1 to external RAM cell 11.
xmov out mem1
mov out2 11[virtual-signal=signal-exclamation-mark]
clr out
; read back the product quantities from external RAM cell 12 to mem1.
clr out
mov out2 12[virtual-signal=signal-question-mark]
nop ; wait for read data to arrive.
xmov mem1 red
clr out
hlt
Code: Select all
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