Sequencer Factory | autonomous crafting | expandable

[Gertibrumm]

Sequencer Factory alias "The Combinated Factory"

*edit: now with wip cpu! in later posts

This in what I have been working on the whole time:
1) no unnessesary production (count accurate)
2) no unused machines
3) demand and autonomous crafting (Independent supply to labs and refueling)
4) maximum belt throughput

The main combinator principal is a closed loop which initiates machines to craft one item-type at a time.

primary supplys are ores, stone, coal, crude oil and water which must be present or on demand delivered to the factory.
secundary products like plates, liquids and solid fuel can be premanufactured to reduce production time of end-products
end products are sequentially produced in a furnace array, in a assembler array, in a chem. plant array.

Everything is connected to a circular belt which takes from storages and outputs and gives to storages and inputs



Basically: IT DOES EVERYTHING FOR ME!!!

main1.jpg (726.77 KiB) Viewed 14008 times

1st.jpg (425.69 KiB) Viewed 14008 times

2nd.jpg (279.88 KiB) Viewed 14008 times

3rd.jpg (122.53 KiB) Viewed 14008 times

4th.jpg (297.24 KiB) Viewed 14008 times

As of now this only works with dry-recipes
That means no chemical plant array as pipes are undrainable if I pump liquids count accurate.
Also I have to manually setup all recipes if the factory wants to produce something.

DISTRIBUTOR and STORAGE

distributorAndStorage.jpg (814.28 KiB) Viewed 14008 times

on the left you can see the intermediate storage.

THE BRAIN

theBrain.jpg (803.12 KiB) Viewed 14008 times

signaling.jpg (265.59 KiB) Viewed 14008 times

The output of the signaling process (left side of brain) is pu into the compiler which calculates all the necessary items except of resources

FURNACE ARRAY

furnaceArray.jpg (703.9 KiB) Viewed 14008 times

Furnaces must be either (1,2,5,10,20 etc) in count due to division of smaller demand numbers

ASSEMBLER ARRAY

assemblerArray.jpg (786.38 KiB) Viewed 14008 times

[IronGator]

Can we have the save?

[brunzenstein]

Can we have the save?

And a more detailed explanation please!
This is grandiose as it is the spirit of the upcoming autonomous industry 4.0 level where machine not only adopt to given needs but active learn to adapt themselves.

[Gertibrumm]

Once I finished the liquid problem ill give you the save!
I just dont want any half baked bread.
Also I will go full throttle on this:

MK II

This is double blue belt with 92% of maximum throughput.

double_blue_belt.jpg (358.26 KiB) Viewed 13870 times

Give me a weak or so to implement changes and additions.
Things are getting less and less complex as I rebuild every time

[brunzenstein]

Once I finished the liquid problem ill give you the save!

The liquid handling is the very interesting - ply share a preview asap

[Gertibrumm]

This morning I was thinking about doing all the different stages of item processing with

- master(controller "The Brain" in cpu form with instructions)(something like this viewtopic.php?f=8&t=23405) and the
- slaves(eg: furnace arrays etc receiving instructions by the master, they can return info like stage of procssing and remaining % etc)
- info_slaves(lamps and displays that display information)

This will make calculations slower than current "hardware" based calculations but in the end pay off due to endless control and flexibility in change of instructions, also liquid processing will be a lot easyer with the instruction pipeline instead of hardware based wire madness

[Gertibrumm]

This evening I built the first part of the single instruction CPU:
- It is running at: 5 ticks for the "jump" instruction(absolute maximum I think) and 8 for the minimum "do_nothing" instruction which can be used as delay with arbitrary duration in ticks. That is for now around 7,5 IPS.
- Basis instructions are eg: "M"1, "D"1234; which loads memory with adress 1 with integer value of 1234, others are "A"dress for IO stuff and "J" signal for jump and "R" for register and so on and so forth.

I anyone has an idea on how I could increase the speed to at least 12 or 15 IPS I would be flattered

instruction_pipeline.jpg (318.66 KiB) Viewed 13747 times

On the left right now only 4 instructions are setup,
bus is on the right side,
memorys/registers are on at the bottom.

Also is it common to clean registers before anything can be written on them?
Also what do I need the stack for? Whats the point of popping and pushing?

[piriform]

I anyone has an idea on how I could increase the speed to at least 12 or 15 IPS I would be flattered

Hard to tell without a blueprint (at least). So many things depend on basic design decisions you've made. In any case, I'd suggest you complete the architecture (i.e. flesh out the instruction set, design the other bits (i.e. ALU, IO etc) before worrying too much about shaving ticks.

Also is it common to clean registers before anything can be written on them?

Only if you expect to compute more than one result

Also what do I need the stack for? Whats the point of popping and pushing?

If you expect your programs to get fair sized (i.e. 100+ instructions) you'd probably want to build in subroutine functionality.
Stack is an easy way of storing the subroutine return addresses, thus allowing nesting and recursion. It can also be used to save values of registers.
ex
do some stuff
Call Routine_X
do other stuff

Routine_X
do some stuff
Push Register A // save A
Call Routine_Y
Pop Register A // restore it
Return
it can also be used to exchange values of registers that do not have a direct path
ex
Push A
Push B
Pop A // A has the contents of B register
Pop B // B has the contents of A register

[Gertibrumm]

This is what I finished yesterday:
finished following instructions:
- Increment/Decrement by n steps takes 2 ticks that is a whopping 30 IPS!!!!
- JUMP instruction takes 3 ticks (20 IPS) to set instruction counter to any desired count
- Delay takes at least 7 ticks due to clunky counter but is accurate (can be improved)
- Memory/Adress/Register READ takes 3 ticks!! (DMA)
- Memory/Adress/Register WRITE takes 4 ticks though at the moment doesnt do anything as nothing is catching the signal

instruction_set_V2 Kopie.jpg (317.04 KiB) Viewed 13655 times

I am going to work on this today:
- MOV will take estimated 5 ticks due to simultaneous read and writeing to any destinations
- Arithmetic will take estimated 5 ticks as it works similar to MOV

sequencerMK2.zip

(1.19 MiB) Downloaded 170 times

here is a save of the MK2
unzip it into the scenarios folder and start a new custom scenario to play
you'll spawn right next to the cpu which is running a loop programm that writes something to memory approximatly every second

[Gertibrumm]

Small changes to the cpu and it is possible to run a MOVE instruction

Details

progamtest.jpg (106.99 KiB) Viewed 13622 times

[Gertibrumm]

As I keep improving the cpu new ideas are coming up:
- single tick instructions (Bus is always used, extremly fast 60 IPS, constrains to keep the whole thing simpler)
- dual bus (for fast instructions and slow ones like external return values)
- improved memory situation with negative values possible by using special memory clear-functions which auto delete whole arrays of memory downwards(the more has to be deleted the faster deletion becomes relative to only deleting one cell)

Testing tomorrow, weekends are picture time ;D maybe save file this time, but I am going to keep you guys up your toes like the devs do!

[Gertibrumm]

Couldn't wait for the weekend ;D
here is the all mighty "Substation-CPU", Challenge: make your CPU faster, smaller, more powerfull
Runs previously explained test program 200 times in 16,8 seconds, thats aproximatly average 47,6 IPS
No ALU in this picture due to no necessity at the moment (memory does addition)

substationCPU.jpg (276.36 KiB) Viewed 12192 times

below memory is the CLEAR command
in the middle above substation is accurate DELAY command
accu charge doesnt survive the night

[Gertibrumm]

Major changes to the instructor, now every command except WRITE command is at its limit
WRITE takes 3 ticks
MOVE takes 3 ticks !!!
CLEAR in Range("C"n, memory1) 4 ticks
READ takes 3 ticks
faster than 3 ticks for certain commands seems hard to implement but is possible. but not necessary as write and read are used so seldom

SubstationCPU_V2.jpg (452.61 KiB) Viewed 12174 times

"Fibonacci Sequence" runs in 8 instructions,
7,3 seconds tell me my calculations to the 44th place which is 701408733,
I measured with stopwatch which tells me inaccurate 7,7 seconds
that would be 18 IPS on the loop

Program in readable syntax could be:

Code: Select all

1 - WRITE Memory 1 with "green" 3  //green 3 is later used for clearing memory 4 to 3 which does not include 3 (clears memory 4)
2 - WRITE Memory 2 with "blue" 1    //blue value will be used for adding up the fibonacci numbers
3 - MOVE Memory 2 to 3
4 - MOVE Memory 3 to 4                  //memory 4 is where fibonacci is put out
5 - CLEAR Memory 4
6 - MOVE Memory 3 to 3
7 - MOVE Memory 2 to 4
8 - CLEAR Memory 4 and JUMP to Instruction 3

as you can see machinecode is much better than C++ or other high level programming language but soooo confusing

[Gertibrumm]

Finished CPU today.
All functions are expandable (further Substaions) like more instructions or more memory, more "F"unctions

Ill post string once I figured out how to export the string
Anyway here it is

SubstationCPU_V3.jpg (533.67 KiB) Viewed 12160 times

[Gertibrumm]

Finished new furnace array yesterday which Ill be using for testing:
Input Output works with two memorys just like the ones in the CPU,
It can set number of used furnaces, input items and collects output item data
+ expandable until blue belts are full

furnaceArrayMK2.jpg (391.56 KiB) Viewed 12144 times

[piriform]

Finished CPU today.

Nice! So do you have any plans for it?

[Gertibrumm]

Well, I am going to control the factory with it! things are less complicated if executed in code instead of hard wired!
Things like the liquid processing, Things like demand keeping and rescheduling, Things like new resource deliveries and production abortion!
Before that, everything had to happen as planned, otherwise the smallest problem created chains of constant problems which had to be constantly adjusted

Once I hooked up other signal processors and filters, I can start implementing some basic factory instructions (thats for the weekend)

[hansinator]

Any news on this?

[Gertibrumm]

Sorry I am working on graduation project/thesis which is taking up all other projects :/ Also lets see what .14/.15 brings, hopefully recipe setting!

Also I am looking at what either piriform or siggboy do about assembler/compiler to ease out the CPU programming workflow which is a pain

But Ill answer any questions coming up as Ill stay active on the forums!

[hansinator]

Well maybe you can just release your CPU blueprint? I'd like to have a look at it.