adressable memory cells.

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adressable memory cells.

Post by Trifonius » Sun Mar 10, 2019 4:27 pm

Hi everyone. What I am about to show you is probably nothing new. I am 96% certain that I could find a similar design by browsing this very forum, probably even a better one. But it's something I made from scratch, and as I am somewhat proud of it, I wanted to share it.

Let's start by looking at what I first designed back in 0.16: a simple memory cell.

Let me explain what's going on:
  • The leftmost decider is the actual storage. It simply sends through its input, and loops back on itself, so the signal is persisted.
  • The rightmost decider is the input. If a certain control signal drops, it will send its input to the storage. This would usually cause the old and new values to be added together, if not for...
  • The arithmetic combinator in the middle. This one inverts the stored value, and sends it back to the input. So whenever we read, we both add the new value and subtract the old value from the old stored value. old+new-old = new. Simple as that.
Advantages and disadvantages:
  • good: seamless output. The storage updates from the old value to the new one within a single tick, making the output fit for e.g. being displayed on nixie tubes (its original purpose).
  • good: noiseless output. no control values to be filtered out later, what you stored is what you get.
  • bad: can't be updated every tick, the cell needs an extra tick to stabilize. This wouldn't be a huge issue, if not for...
  • bad: the control signal. If it drops for a signal tick, the cell will read. If it drops for more than one tick, though, (e.g. by being disconnected), the cell will start glitching out.
After losing the design between 0.16 and 0.17, I remade it yesterday, and posted it on reddit as part of a belt reader module. ... t_counter/
It was in the process of reacting to one of the comments that I "invented" memory addresses. You can find that intermediate design in the reddit post. Once I realized what I had done, I refined it to have adressable read access, and this is the result:

The blueprint is for a more compact version. Let's explain its inner workings once more (apologies for my image editing skills):
  • The middle arithmetic combinator determines the adress of the cell. It subtracts one from the adress of the row above, resulting in an adress one bigger than the row above. Since these are negative numbers, sending the positive adress across either the write or read control cables will result in the sum being 0 on those combinators, triggering a read or write action.
  • Speaking of writing, the three leftmost combinators are nothing new. The writing combinator now checks if A=0, so whether the sum of the incoming (positive) adress and the local (negative) adress is 0, and updates the storage if this is the case.
  • The second combinator from the right merely serves to combine the storage and the adress, as we don't have three inputs on the rightmost combinator, the read acces point. These three signals (the local adress, the adress sent across the read control line, and the storage) need to all be kept separate. Any A value leaking into the storage would corrupt the cell, and we can't attach the local adress to the read control line as that would mess up all other cells. So when the local adress matches the adress sent across the read control line, the read combinator outputs the stored value across the read output line.
So there we have it! Working adressed memory in factorio. Some additional notes:
  • It takes three ticks for an updated value to reach the read combinator. Any read requests sent less than three ticks after a write will get the old value.
  • Any signal can be stored, save A, which designates the adress. If you desperately need the entire alphabet, use fish as adresses.
  • Once again, leave one tick between two writes to the same cell.
  • You could combine the read control and read output line, but that would force you to either leave one tick between two reads, or filter out adresses from the output. With two wires, our output is sparkly clean.
So that's what I came up with. If you learned something from this, pleased to help you. If you have a better design, feel free to show it off in the comments.

The Eriksonn
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Re: adressable memory cells.

Post by The Eriksonn » Tue Mar 12, 2019 2:56 pm

This is quite similar to my RAM module for my combinator computer. Except that my version relies more on external pulses rather than internal pre-processing(ie it doesnt auto-override like yours do but for me it is fine as it it takes longer to pre-process the correct input anyways)

The rightmost one is the input. (G=x => Everything) where x is the adress of this module, G is the variable for what adress to save to.
The right/middle one is the actual memory cell. (Black=0 => I) holds the memory in the variable "I" until the black reset signal is passed in
The left/middle is for filtering the output using the value obtained from the leftmost decider.(each*I = each)
The leftmost is for filtering the output values by adress(each=x => each)
the reason for the strange output system is so that i can output multiple values at once.

So as an example:
Save number 15 into adress 3: Step 1:(G=3,Black=1) Step 2:(G=3,I=15) (column 4)
Save number -23 into adress 4: (G=4,Black=1) (G=4,I=-23) (column 4)

Load adress 3 into variable A and adress 4 into variable B:(A=3,B=4)(column 1)
Result(column2): A= 15,B=-23 (and also some really strage I value that needs to be filtered out)

Reset everything: (black=1)(column 3)

2019-03-12.png (3.13 MiB) Viewed 517 times

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