Delayed Pulse Generator

[Amegatron]

Hello there!

I recently implemented a memory array scheme found on reddit and once I finished it, I realised I need a delayed pulse generator to send data to memory. In my case the input data must stay for at least 4 ticks to become written into a memory cell. 4 is not so many and I just inserted 2 more passers in a simplest pulse generator. But after that I began thinking about how to delay a signal for a specified time without placing more and more intermediate pass-through deciders just for increasing the delay when signal-inverter would come to outputing device.

Having spent a couple of hours I came to this schema which is working basically, but it is pretty far from ideal. Here it is.

Click to view the schema

As you may notice in side-notes it is impossible in this layout to specify exact number of ticks the signal will stay in output. In this case actual ticks equal to 4, 7, 10, 13 and so on (N*3-2).

So I wonder, has anybody come to a better schema for a delayed signal transfer, which is customizable and allows more precise delays?

[piriform]

I'm not sure if you are dealing with binary signals or whether you are looking to delay or extend the signal, but this may be of help

delay.jpg (28.63 KiB) Viewed 8311 times

Description
1. Test signal generator consisting of a clock, and two deciders that generate blue =1 and green =5 signals on tick 5 (green is the signal)
2. SR flip flop ( Blue>Red; Blue = 1)
3. Reset for SR consisting of a clock ( Blue < N; Blue = count and Blue = N; Red = count) (N is the desired extender)
4. Signal gate consisting of a register (Red=0; Everything= count) and the gate (Green * Blue ;Green)
You could probably simplify this when dealing with binary signals by omitting #4 and using the actual signal instead of blue.
BTW why are you using such a complicated memory design?

[Amegatron]

I'm not sure if you are dealing with binary signals or whether you are looking to delay or extend the signal, but this may be of help
...
BTW why are you using such a complicated memory design?

I've found a memory array scheme on reddit https://www.reddit.com/r/factorio/comme ... _array_v2/ and implemented it with some bugfixes. It is working but it turned out that it does not write data to a cell if it is present in the input for only 1 tick. After some experiments I found out it needs at least 4 ticks. And yes, it writes the whole signal (not just binary) minus some reserved signals needed for "management" of this memory.

I did not find any other schemes for memory arrays though :/

Considering your idea I cannot fully understand it, sorry :/ Could you please make a blueprint for it? In my version I also use timer (or to say correctly "delayed" timer), but other stuff which is needed to reset the timer upon completion and singal reset take a bunch of excess ticks :/

[Amegatron]

Seems now I'm in a right direction - got an idea of a SR-latch to start/stop the clock
P.S. Also found a bug in my memory array. Now 1 tick is enough for signal to be written to a cell =) Row/Column calculation blocks were out of sync.

[piriform]

Seems now I'm in a right direction - got an idea of a SR-latch to start/stop the clock

Let me know if you still need the blueprint

If you are just looking for a memory design, you might want to consider this

RAM.jpg (20.1 KiB) Viewed 8199 times

This is one memory cell. Additional ones can be daisy chained using red wires . It reads in 1 tick and writes in 2. The only trick (if you can call it that), when writing, address Cnn and RED must be presented simultaneously followed by address and Data. (i.e clear then load). Setup can be bit of a pain as each cell must have explicitly assigned address (i.e. A=1,C=1...). At some point I may write a script for that.

[Amegatron]

Let me know if you still need the blueprint

Thanks For now I don't know for sure what memory I need. In variant I have now data is read in 5 ticks but I have no need to specify each cell's number - the "controller" calculates cell's row and column so that the needed cell and only it receives BLUE=0 which means that this cell is addressed.

Again, can't say what will be crucial for me, because I am only designing my first "device" =) (I want to make a device similar to ColonelWill's Hall of Fame - a screen which displays strings (user names) one after one)

[Amegatron]

Seems now I'm in a right direction - got an idea of a SR-latch to start/stop the clock

Let me know if you still need the blueprint

If you are just looking for a memory design, you might want to consider this

RAM.jpg

This is one memory cell. Additional ones can be daisy chained using red wires . It reads in 1 tick and writes in 2. The only trick (if you can call it that), when writing, address Cnn and RED must be presented simultaneously followed by address and Data. (i.e clear then load). Setup can be bit of a pain as each cell must have explicitly assigned address (i.e. A=1,C=1...). At some point I may write a script for that.

Sorry for maybe necroposting, but I returned to Factorio couple a days ago and started to play with combinators again. Having tried some variations of memory cells, I recalled your version and tried to implement it. The cell itself is pretty straightforward, but it took me some efforts to build a test writer Here is what I've got:

blueprint

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I'm not sure the writer is optimal, it looks pretty ugly and maybe overcomplicated All it does is when red signal appears in input, it firstly sends it together with the write-address signal for 1 tick, after that the data is sent to the array without red signal, also for 1 tick. In this example BLUE signal is used as write-address in input, and GREEN signal is a read-address in output.

[piriform]

Sorry for the late reply (didn't see your post )
You could consider something like this

RAMctl.gif (286.2 KiB) Viewed 7229 times

The 3 combinators on the left are a one short that provides a pulse of data,address and clear. In practice they'd be replaced by your circuitry.
Two arithmetic combinators to the right are set to address =address*clear, data=data*clear thus extending the address and data signals by 1 tick.
So, tick one: address,data,clear are asserted on the write bus. Data is ignored as clear signal wipes everything. Tick two, only address and data are asserted, and data is written into the correct memory cell.

[Amegatron]

Sorry for the late reply (didn't see your post )
You could consider something like this
The 3 combinators on the left are a one short that provides a pulse of data,address and clear. In practice they'd be replaced by your circuitry.
Two arithmetic combinators to the right are set to address =address*clear, data=data*clear thus extending the address and data signals by 1 tick.
So, tick one: address,data,clear are asserted on the write bus. Data is ignored as clear signal wipes everything. Tick two, only address and data are asserted, and data is written into the correct memory cell.

Damn, I now look at my version and ask myself: "wth is going on there? why so many combinators?" But I had to change your writer a little bit. I still have 2 arithmetic comb-s, but one is (*)*clear=>(*), onther is clear*-1=>clear, because I assume I'll have to write arbitrary data to a cell, not just a predefined signal. In your case those 2 comb-s just pass "data" (which I suppose is a predefined signal?) and "address" further, so "clear" is lost at 2nd tick. But in my case I just filter out "clear" signal on the second tick. Nevertheless, thank you for opening my eyes on it

Memory Array

result.jpg (124.69 KiB) Viewed 7204 times

[piriform]

because I assume I'll have to write arbitrary data to a cell, not just a predefined signal. In your case those 2 comb-s just pass "data" (which I suppose is a predefined signal?

Well you know how it is: Sometimes you can't see the trees for the forest
Yes, "data" in my case is a fixed signal type. I suppose I should have known better, as the virtual 2 you used, was a definite hint.