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For each of the input signals (only green channel input ticked! => 2 input signals) the condition is true.
Thus it should output A=2 not A=3.

Maybe the current implementation is intended, but in combination with the possiblity to toggle R and G input it sure isn't intuitive .
Edit: typo

exabyte wrote: Mon Nov 04, 2024 1:09 pm For each of the input signals (only green channel input ticked! => 2 input signals) the condition is true.
Thus it should output A=3 not A=2.

I take it you mean "A=2 not A=3"?

Loewchen wrote: Mon Nov 04, 2024 1:43 pm

exabyte wrote: Mon Nov 04, 2024 1:09 pm For each of the input signals (only green channel input ticked! => 2 input signals) the condition is true.
Thus it should output A=3 not A=2.

I take it you mean "A=2 not A=3"?

Yes thx, I've updated the description

3 is correct.
A "missing" signal isn't actually missing. It is zero. Combinators just ignore signals with value 0 for performance, I'd assume, unless something specifically checks against them in which case they are "0".

So when the combinator evaluates the "each" on red and hits the fast inserters it checks for them on green and gets "0".

speed mod: 4 <= 11 which outputs A = 1
assembler: 2 <= 6 which outputs A = 1
inserter: 0 <= 2 which outputs A = 1

Final output from the combinator is A=3

3 is correct. If you want 2, you can change the conditions into `Each[G] <= Each[R] AND Each[G] != 0`

boskid wrote: Mon Nov 04, 2024 3:22 pm 3 is correct. If you want 2, you can change the conditions into `Each[G] <= Each[R] AND Each[G] != 0`

Thanks maybe there is a way to convey this a bit better for circuit network newbies =)