there is more to it than that.seePyou wrote:"The memory transfer speed itself is not that slow, but the waiting (latency) time between ordering and receiving it is. "
Doesn't that describe the memory value "CAS Latency" ? Or am I wrong? If I'm not wrong, why have memory modules gone to such a high CAS latency value in this day and age? I am a senior in the world of PC and gaming, so I do remember the times when memory modules with 4 CAS latency were prized! Now they are non-existent.
CAS refers to reads withing the same row in the DRAM bank (data local to the previous read). Once you switch rows you need to take into account the row switch itself. In random unpredictable accesses this will start dominating.
Because memory modules have multiple internal banks, and data can be output from one during access latency for another, the output pins can be kept 100% busy regardless of the CAS latency through pipelining; the maximum attainable bandwidth is determined solely by the clock speed. Unfortunately, this maximum bandwidth can only be attained if the address of the data to be read is known long enough in advance; if the address of the data being accessed is not predictable, pipeline stalls can occur, resulting in a loss of bandwidth. For a completely unknown memory access (AKA Random access), the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it. Due to spatial locality, however, it is common to access several words in the same row. In this case, the CAS latency alone determines the elapsed time.