Multi-Signal Clocked Addressable Memory Cell (Save/1tick)
Posted: Mon Jun 03, 2019 9:14 pm
I recently created an all signal SR Latch after being inspired by some of the great combinator creations here. It was great for my first creation but I soon realized that its set/reset nature was not very useful in many cases and overall the latch was a little over-designed. 
However, I had a LOT of fun making it and wanted to create better versions. Therefore, I started working on a clocked memory module. The idea was that the module would have two separate input wires, one for the clock signal and other for data. Whenever the clock wire has any signal, the module should load whatever signals are present on the data wire and output them at its output until the next clock signal changes its memory.
TLDR:
I started with a decider combinator feeding into itself when a signal S=0. This way, I can control when this combinator feeds itself.
To prevent a continuous signal from causing an infinite loop (loop that increments till the signal is zero), I had to stop the above combinator from feeding itself when there was a signal at the input.
For this, I used another decider combinator that allows data to pass through only when S!=0 (S is not 0)
This way, I could use the S signal as a flag for when to let data into the memory. Just like a clock signal...!
When S=1 data is allowed to flow through the 2nd combinator and the 1st one doesn't loop due to its configuration.
When S=0 data is not allowed to flow through and never interferes with the memory combinator's loop.
Since I use the S signal to control the working of this module, this signal should never be a part of the input data. It should instead always be separate from the data line, i.e. on its own wire.
Notice that now even the S signal can enter the memory loop. In fact, it is entered twice, once directly from the clock signal wire and then by passing through the 2nd combinator. This causes the memory loop to never start in the 1st combinator since S=0 is not satisfied even when the S signal in the clock wire is removed.
To solve this, I simply added an arithmetic combinator to cancel the S signal obtained from the 2nd combinator.
This 3rd combinator serves only to remove all S values from both the clock and data input signals.
Now by connecting a "data" source on the 2nd combinator, I can use the S signal to save this into the memory.
When the S signal is non-zero, this module saves whatever is on the data wire (here green wire from constant combinator). This means that to clear the memory, I can simply pass nothing on the data wire while the clock signal S has a non-zero value.
Making this Addressable
Notice that the "data" is allowed to enter the module when the S signal is non-zero and it is saved in the loop when S=0. This means that if we change the two conditions for our 1st and 2nd combinators to only allow specific values of S, we can make this addressable.
This can be done very simply. Here I show this by using 10 as the only S value that the module accepts data for :-
The final memory cell looks as such
However, I had a LOT of fun making it and wanted to create better versions. Therefore, I started working on a clocked memory module. The idea was that the module would have two separate input wires, one for the clock signal and other for data. Whenever the clock wire has any signal, the module should load whatever signals are present on the data wire and output them at its output until the next clock signal changes its memory.
TLDR:
Single Address (save when S is non-zero)
Addressable with address x (change conditions to S!=x in 1st combinator and S=x in 2nd)
I started with a decider combinator feeding into itself when a signal S=0. This way, I can control when this combinator feeds itself.
- 1.png (223.86 KiB) Viewed 11096 times
To prevent a continuous signal from causing an infinite loop (loop that increments till the signal is zero), I had to stop the above combinator from feeding itself when there was a signal at the input.
For this, I used another decider combinator that allows data to pass through only when S!=0 (S is not 0)
- 2.png (242.84 KiB) Viewed 11096 times
This way, I could use the S signal as a flag for when to let data into the memory. Just like a clock signal...!
When S=1 data is allowed to flow through the 2nd combinator and the 1st one doesn't loop due to its configuration.
When S=0 data is not allowed to flow through and never interferes with the memory combinator's loop.
Since I use the S signal to control the working of this module, this signal should never be a part of the input data. It should instead always be separate from the data line, i.e. on its own wire.
- 3.png (391.48 KiB) Viewed 11096 times
Notice that now even the S signal can enter the memory loop. In fact, it is entered twice, once directly from the clock signal wire and then by passing through the 2nd combinator. This causes the memory loop to never start in the 1st combinator since S=0 is not satisfied even when the S signal in the clock wire is removed.
To solve this, I simply added an arithmetic combinator to cancel the S signal obtained from the 2nd combinator.
This 3rd combinator serves only to remove all S values from both the clock and data input signals.
- 4.png (526.5 KiB) Viewed 11096 times
Now by connecting a "data" source on the 2nd combinator, I can use the S signal to save this into the memory.
When the S signal is non-zero, this module saves whatever is on the data wire (here green wire from constant combinator). This means that to clear the memory, I can simply pass nothing on the data wire while the clock signal S has a non-zero value.
- 5.png (719.67 KiB) Viewed 11096 times
- 6.png (641.09 KiB) Viewed 11096 times
Making this Addressable
Notice that the "data" is allowed to enter the module when the S signal is non-zero and it is saved in the loop when S=0. This means that if we change the two conditions for our 1st and 2nd combinators to only allow specific values of S, we can make this addressable.
This can be done very simply. Here I show this by using 10 as the only S value that the module accepts data for :-
- qf.png (1.37 MiB) Viewed 11096 times
The final memory cell looks as such
- Annotation 2019-06-04 013734.png (1.76 MiB) Viewed 11096 times