Multi-Signal Clocked Addressable Memory Cell (Save/1tick)

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jaideep
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Multi-Signal Clocked Addressable Memory Cell (Save/1tick)

Post by jaideep »

I recently created an all signal SR Latch after being inspired by some of the great combinator creations here. It was great for my first creation but I soon realized that its set/reset nature was not very useful in many cases and overall the latch was a little over-designed. :D

However, I had a LOT of fun making it and wanted to create better versions. Therefore, I started working on a clocked memory module. The idea was that the module would have two separate input wires, one for the clock signal and other for data. Whenever the clock wire has any signal, the module should load whatever signals are present on the data wire and output them at its output until the next clock signal changes its memory.

TLDR:
Single Address (save when S is non-zero)


Addressable with address x (change conditions to S!=x in 1st combinator and S=x in 2nd)

I started with a decider combinator feeding into itself when a signal S=0. This way, I can control when this combinator feeds itself.
1.png
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To prevent a continuous signal from causing an infinite loop (loop that increments till the signal is zero), I had to stop the above combinator from feeding itself when there was a signal at the input.
For this, I used another decider combinator that allows data to pass through only when S!=0 (S is not 0)
2.png
2.png (242.84 KiB) Viewed 3438 times

This way, I could use the S signal as a flag for when to let data into the memory. Just like a clock signal...!
When S=1 data is allowed to flow through the 2nd combinator and the 1st one doesn't loop due to its configuration.
When S=0 data is not allowed to flow through and never interferes with the memory combinator's loop.
Since I use the S signal to control the working of this module, this signal should never be a part of the input data. It should instead always be separate from the data line, i.e. on its own wire.
3.png
3.png (391.48 KiB) Viewed 3438 times

Notice that now even the S signal can enter the memory loop. In fact, it is entered twice, once directly from the clock signal wire and then by passing through the 2nd combinator. This causes the memory loop to never start in the 1st combinator since S=0 is not satisfied even when the S signal in the clock wire is removed.
To solve this, I simply added an arithmetic combinator to cancel the S signal obtained from the 2nd combinator.
This 3rd combinator serves only to remove all S values from both the clock and data input signals.
4.png
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Now by connecting a "data" source on the 2nd combinator, I can use the S signal to save this into the memory.
When the S signal is non-zero, this module saves whatever is on the data wire (here green wire from constant combinator). This means that to clear the memory, I can simply pass nothing on the data wire while the clock signal S has a non-zero value.
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6.png
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Making this Addressable

Notice that the "data" is allowed to enter the module when the S signal is non-zero and it is saved in the loop when S=0. This means that if we change the two conditions for our 1st and 2nd combinators to only allow specific values of S, we can make this addressable.
This can be done very simply. Here I show this by using 10 as the only S value that the module accepts data for :-
qf.png
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The final memory cell looks as such
Annotation 2019-06-04 013734.png
Annotation 2019-06-04 013734.png (1.76 MiB) Viewed 3438 times

DOSorDIE
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Re: Multi-Signal Clocked Addressable Memory Cell (Save/1tick)

Post by DOSorDIE »

Absolut Genius!

I have 1 question:
It is possible to set the Adress in the memory per constant combinator?
So that its easy to set the memory to as example 8.

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Optera
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Re: Multi-Signal Clocked Addressable Memory Cell (Save/1tick)

Post by Optera »

Being more understandable and easily addressable certainly seems like an advantage over the old design from Xknight: viewtopic.php?f=193&t=13776&start=40#p198182

cid0rz
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Re: Multi-Signal Clocked Addressable Memory Cell (Save/1tick)

Post by cid0rz »

Very nice design! I was again tinkering with combinators and thought I needed an addressable memory bank, I found this recent post and It works really well. I'm working on updating some old circuits and they are from when there was no != operator on the combis so I think Ill be changing a lot of memory cells to this system since is is very easy to clear.

I've done a couple of useful contraptions I hope someone finds useful too:

Addressable memory bank (5cells but expandable)

4 wire system as in the figure
Write data is the signal to be written in the cell
Write address is the memory address where u want to save it (I chose signal M for the address since S is important for me elsewhere so I may need to store S)
Read address is the memory address you want to be in the output wire
Read data is the output wire of the memory bank + M memory address where it was stored (you can remove it with an additional combinator but i prefer to know where data was stored and remove it when I'm going to use the data
the light turn on if the memory is currently in used
It uses 1 tick for any operation and you can operate it even manually, is a very straightforward and safe design.

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FIFO(kinda)

This is just a series of cells cabled in a special way. They are all addressed M=1. For this design to work you need 1tick M pulses on pulse input. I provided a dummy pulse generator for testing purposes. For each pulse, all memories will move the result to the following cell and the first one will load from the signal wire. The reading is independent, you could leave only 1 reading at the end of the queue. This I thought about it while searching for ways to cross schedules. I was thinking also on a way to do a LIFO but I don't like the solutions I come up with.

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PD sometimes i mark "use colors" on the lights just to make them less bright when i know no color signals will be on the circuit so beware if u use colors u may want to uncheck those boxes.

Any suggestion, doubt, critique etc. is very welcomed!

Cheers!

cid0rz
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Re: Multi-Signal Clocked Addressable Memory Cell (Save/1tick)

Post by cid0rz »

Hi and let me proudly present my implementation of a LIFO queue with your cells.

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