Factorio Forums

Posted: **Thu Aug 06, 2015 10:17 pm**

Hi all,

I am proud to present the most compact memory cell I ever created. It requires only 1,08333 combinators per cell in average.
You might ask: "how is it possible to use a fractional number of combinators per cell?"
The answer is simple: several different memory cells share the same address combinator, and they differ only in control signal for every cell.

The only problem with this setup is complicated read/write operation. But they still can be done.

First of all, we need to calculate real address value, for example: we should write something to cell #123, and each cell-group consists of 10 cells, so the result address will be group #12 and cell #3. Also, cell address should be transformed to the control signal using alphabet (cell #1 - signal "0", cell #2 - signal "1", and so on. You can use any items in alphabet, it is preferable to use useless items). After this we can perform read/write operations.

I want to see write operation

I want to see read operation

Putting all together

It is important to mention, that this build is designed for pulse read-write operation, so it won't work if you connect it to a chest. I used two combined cells, where each consists of 5 combinators. This setup was selected because it is easy to build and i don't need to create several screenshots. But the optimal size of combined cells is 12.

Wait a minute. Could you explain more

And the last but very important information: THIS BUILD IS REALLY VERY VERY SLOW.
But you will have lots of fun while creating something similiar

Posted: **Mon Feb 22, 2016 5:42 pm**

I can beat that! (in lack of SPEED that is).
Behold, a Delay Line memory (proof of concept)
Needs 1 combinator per cell (+ ahem, controller)
Reads and Writes at 1 tick.
Access time N/2 (average)! (so 1000 cells, 500 ticks

)
But the biggest problem is I cannot think of a single viable use for it.

Posted: **Mon Feb 22, 2016 6:58 pm**

First post: Thu Aug 06, 2015 10:17 pm
Second post: Mon Feb 22, 2016 5:42 pm

After more than 6 month I finally received an answer

Your idea is not so new as you think...
I am using almost the same build in CPU inside each cache line, but conditional combinators in your design are replaced with (Each * -1).
The main advantage of this build is incredibly simple batch copy-paste operation.
For example: you have cache line which consist of 10 elements.
For some reason you decided to upload new cache line.
The only thing you need to do in this case is to send the same signal (which contains source and target cache line index) 10 times in a row, and everything will be copied from source cache line to destination line.
This is very nice

Also, thanks to "Each * -1" single cell overwriting is very simple.

: 1.png (335.15 KiB) Viewed 12323 times

Posted: **Mon Feb 22, 2016 7:31 pm**

Yes, I'm relatively new at this and the combinator stuff is scattered all over. Would be nice if there was a dedicated thread.
Interesting design , I'll have to try it. Mine was more of a "I wonder if this will actually work". Well, it does ....
Good luck with the CPU, I think there is place for a fast process controller in Factorio.

edit I added the diagram of delay memory for ref.

Posted: **Mon Sep 05, 2016 10:31 pm**

Hi, Ihope not to arrive too late to this topic. I was working today and I wanted some compact memory cell. I searched a bit but as I've been going crazy with combinators lately I started from 0 and came up with this solution:

: memorycells.jpg (434.75 KiB) Viewed 9392 times

Top one is expanded for better understanding and bottom one is the same but in compact format and wiring.
The concept is similar to yours, I just use 1 arithmetic combinator to store the information, you can store as many signas as you want in a wire xD. Even inf you loose electricity the signal will be there. The reset of the memory took me a bit more. In the compact version I added the decider combinator top left just not to wire the reset signal 2 times. You can write (1 tick)and reset (I think is about 3 ticks but I havent checked xD) quite fast. I put the blueprint so you can test and tell me what do you think. I programmed it to set with "S signal+what you want to store" and to reset with R signal. Of course for multiple memory cells you shoud add an address that can be an additional multiplication before the cell so if it carries the key signal it will be written there. The advantage is with R signal you can delete as many cells as you want in (3 or 4 ticks). To read i imagine you can do the same, placing aritmethics downstream with address check and Read signal. Can you also please your blueprints so i can test?

I used KBM for the blueprints, I think you just open, copy the string and paste it xD

Posted: **Tue Sep 06, 2016 12:02 am**

I did a modification to allow Read Write and Erase quite easily. Read and Write are done in 1 tick (I think) Erase is the same unknown amount as before

. So Here there is the demo:

: WREdemo.jpg (566.74 KiB) Viewed 9381 times

I didnt compacted the "~~write~~ Read section" but it can be customized easily. Now it works like that:

WRITE: to write an instruction you have to send W ADRESSl + signal to store
ERASE: to erase only E
READ: you have to send R, -W, -ADRESS (-1 of these signals)

I'm pretty satisfied with it, Ill try to apply somewhere xDD

Posted: **Thu Sep 15, 2016 9:26 pm**

This are 2 blocks (without the constant combinators on top) of 210 32bit words (840 bytes), so 1680 bytes of memory in total. Each block is 15x3 tiles in size and contains 21 combinators. Can be extended until you run out of addresses, or, rather the game runs out of memory itself.
Can write any 32bit value in 4 ticks, read in 3 ticks, pipelineable.

Of the 21 combinators only one is used to store the information, the rest are address selectors and read/write mechanics. Some functions are redundant to achieve the read/write speed which still is kinda slow.
I avoided calculating the block for each address (modulo operations just take too long) by using deciders and constants.
Selecting one specific item and it's value from the memory cell was kinda tricky. Might be room for improvement there. Also reading and writing at the same time is not possible nor is reading more than one address at a time.

I could move the address calculations and some functions out of the memory block but this would add even more delay to the already slow access.

edit:

Input: Left Pole: green wire: Address (Red signal (anything > 0)), red wire: Data (Black signal), Write (Green signal = -1)
Output: Right Pole: red wire (Black signal)

Blueprint

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